rebase

Fix barriers in level3_thread

Use wait-for-event to not spin in the blas_lock

Add syr benchmark

Make rpcc() on arm64 get closer to what x86 returns

Apply MinGW AVX512 compilation fix to fortran options as well

Adjust SkylakeX GEMM3M parameters, add an AVX512 STRMM kernel and fix performance bugs in AVX2 s/c/z GEMM

Add Neoverse-N1 core

The Arm implementation of rpcc() uses the architected timer
which is defined by the SBSA to be between 10-400MHz. These numbers
are much smaller than the cycle counter frequency used by x86. Make
the numbers closer by shifting the cycle counter up by the number of
leading zeros in the cntfrq_el0 register which gets us closer to a
noraml cpu clock cycle range.

The implementation is a hybird of the ARMV8 one with some of the
improved TX2 rountines along with specifying -march=v8.2-a

original issue was #1708, I see now that the same problem affects gfortran compilation. The underlying issue is said to be fixed (but not yet released) on all branches of gcc as of a few days ago but it will certainly take time to reach mingw/msys.

Always select ARMV8 parameters for big servers when cpu is TSV110 or EMAG8180

rebase

[WIP] Add support for Ampere EMAG8180 ARMV8 cpu

[OpenBlas]:benchmark/copy.c has time，x,y data loop problems

Apply fix from Reference-LAPACK PR 390

Add proper defaults for the IxMIN/IxMAX kernels on mips64 and power

the fallbacks from Makefile.L1 assume a combined source for absolute value and non-absolute (with ifdef USE_ABS) but here we have separate implementations

the fallbacks from Makefile.L1 assume a combined source for absolute value and non-absolute (with ifdef USE_ABS) but here we have separate implementations

rebase

Fix handling of ppc endianness