For small register blockings that are too small to fill up vector
registers with column vectors, we currently use a generic code block.
Replace that with instantiations of the generic code as individual
functions, so that the compiler can optimize each one separately.

Signed-off-by: Marius Hillenbrand <mhillen@linux.ibm.com>

Improve performance of SGEMM and DGEMM on z14 and z15 by unrolling and
interleaving the inner loop of the SGEMM 16x4 and DGEMM 8x4 blocks.
Specifically, we explicitly interleave vector register loads and
computation of two iterations.

Note that this change only adds one C function, since SGEMM 16x4 and
DGEMM 8x4 actually map to the same C code: they both hold intermediate
results in a 4x4 grid of vector registers, and the C implementation is
built around that.

Signed-off-by: Marius Hillenbrand <mhillen@linux.ibm.com>

Fix GCC ubsan warnings in x86_64 complex dot and gemv_t kernels

Fix lapack-tests linking to a suffixed libopenblas in cmake builds

fixes GCC ubsan warning in the BLAS tests

fixes GCC ubsan report in the BLAS tests

fixes GCC ubsan report of "left shift of negative value -2" in the BLAS tests

fixes GCC ubsan report of "left shift of negative value -2" in the BLAS tests

rebase

Add SYMBOLPREFIX and/or SYMBOLSUFFIX to cblas prototypes

Protect against inadvertent activation of USE_CUDA

Use systemcfg APIs for CPU detection on AIX

AIX libc already provides ready access to an integer that contains a bit
identifying the CPU it's running on, so there's no need to call a
program and grep its output. Additionally, prtconf is not available in
the PASE runtime, which provides an AIX emulation layer on the IBM i
operating system.

The AIX systemcfg.h also provides macro definitions like POWER_8,
POWER_9, etc for all the bits defining the CPUs as well as macros like
__power_8(), __power_9_andup() that return booleans, but I did not use
them. Since these macros depend on the level of the OS in which it is
built, they may not be defined and instead the associated hex literals
are used directly.

Reorganize OpenMP build options for POWER and allow compiling for POWER9 with old gcc

dgemv optimization for POWER10

Making use of new vector pair POWER10 instructions in dgemv_n and dgemv_t.
Also adding a new block 4x128 to make use of Matrix-Multiply Assist (MMA)
feature introduced in POWER ISA v3.1.  Tested on simulator and there
are no new test failures.

rebase

Adjust A53 SGEMM parameters to reflect recent switch to 8x8 kernel

Add AMD Renoir/Matisse cpu autodetection and preliminary support for Zen3

Fix compilation issues with clang on POWER

also support AMD family 22 Jaguar/Puma as Bobcat

also remap erroneous family 16 entry to BOBCAT and reclaim erroneous family 25 "Barcelona" for Zen3

As gcc defaults to -malign-power, removing that option. Also
adding -fno-integrated-as to use GNU assembler for powerpc
assembly optimization files. Fixed other compilation errors
reported in dgemv_t.c file.

ARM64: Add THUNDERX3T110 Target

Move potrf_parallel.c from lapack/getrf to lapack/potrf where it belongs

Fix to store results in correct order for POWER10 GEMM kernels

must have misplaced this in ../getrf when I made that change in March 2018 (40160ff)
the only changes since then were 
RFC : Add half precision gemm for bfloat16 in OpenBLAS Rajalakshmi Srinivasaraghavan
Rajalakshmi Srinivasaraghavan committed on 14 Apr 2020 as 7ebbb50

    Change _STDC_VERSION__ to __STDC_VERSION__ 
Zhiyong Dang committed on 11 May 2018 as 3716267

There is a recent compiler change in __builtin_mma_disassemble_acc() which
affects the order of storing result in POWER10. Also removing new LDFLAG
-mno-power10-stub as it is handled by linker automatically.

WIP Further fixes for 32bit POWER8

Fix alignment errors in the power8 saxpy kernel

Fixes for compilation on POWER with PGI compilers