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OpenBLAS/kernel/power/imax.S

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  1. /*********************************************************************/

  2. /* Copyright 2009, 2010 The University of Texas at Austin.           */

  3. /* All rights reserved.                                              */

  4. /*                                                                   */

  5. /* Redistribution and use in source and binary forms, with or        */

  6. /* without modification, are permitted provided that the following   */

  7. /* conditions are met:                                               */

  8. /*                                                                   */

  9. /*   1. Redistributions of source code must retain the above         */

  10. /*      copyright notice, this list of conditions and the following  */

  11. /*      disclaimer.                                                  */

  12. /*                                                                   */

  13. /*   2. Redistributions in binary form must reproduce the above      */

  14. /*      copyright notice, this list of conditions and the following  */

  15. /*      disclaimer in the documentation and/or other materials       */

  16. /*      provided with the distribution.                              */

  17. /*                                                                   */

  18. /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */

  19. /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */

  20. /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */

  21. /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */

  22. /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */

  23. /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */

  24. /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */

  25. /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */

  26. /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */

  27. /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */

  28. /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */

  29. /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */

  30. /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */

  31. /*    POSSIBILITY OF SUCH DAMAGE.                                    */

  32. /*                                                                   */

  33. /* The views and conclusions contained in the software and           */

  34. /* documentation are those of the authors and should not be          */

  35. /* interpreted as representing official policies, either expressed   */

  36. /* or implied, of The University of Texas at Austin.                 */

  37. /*********************************************************************/

  38. 

  39. #define ASSEMBLER

  40. #include "common.h"

  41. 	

  42. #define RET	r3

  43. #define X	r4

  44. #define INCX	r5	

  45. 

  46. #define N	r6

  47. #define NN	r7

  48. #define XX	r8

  49. #define PREA	r9

  50. 

  51. #define FZERO	f1

  52. 

  53. #define STACKSIZE 160

  54. 

  55. 	PROLOGUE

  56. 	PROFCODE

  57. 

  58. 	addi	SP, SP, -STACKSIZE

  59. 	li	r0,   0

  60. 

  61. 	stfd	f14,    0(SP)

  62. 	stfd	f15,    8(SP)

  63. 	stfd	f16,   16(SP)

  64. 	stfd	f17,   24(SP)

  65. 

  66. 	stfd	f18,   32(SP)

  67. 	stfd	f19,   40(SP)

  68. 	stfd	f20,   48(SP)

  69. 	stfd	f21,   56(SP)

  70. 

  71. 	stfd	f22,   64(SP)

  72. 	stfd	f23,   72(SP)

  73. 	stfd	f24,   80(SP)

  74. 	stfd	f25,   88(SP)

  75. 

  76. 	stfd	f26,   96(SP)

  77. 	stfd	f27,  104(SP)

  78. 	stfd	f28,  112(SP)

  79. 	stfd	f29,  120(SP)

  80. 

  81. 	stfd	f30,  128(SP)

  82. 	stfd	f31,  136(SP)

  83. 

  84. 	stw	r0,   144(SP)

  85. 	lfs	FZERO,144(SP)

  86. 

  87. #ifdef F_INTERFACE

  88. 	LDINT	N,    0(r3)

  89. 	LDINT	INCX, 0(INCX)

  90. #else

  91. 	mr	N, r3

  92. #endif

  93. 

  94. 	li	RET, 0

  95. 	mr	NN, N

  96. 	mr	XX, X

  97. 

  98. 	slwi	INCX, INCX, BASE_SHIFT

  99. 

  100. 	li	PREA, L1_PREFETCHSIZE

  101. 

  102. 	cmpwi	cr0, N, 0

  103. 	ble-	LL(9999)

  104. 	cmpwi	cr0, INCX, 0

  105. 	ble-	LL(9999)

  106. 

  107. 	LFD	f1, 0 * SIZE(X)

  108. 	add	X, X, INCX

  109. 

  110. 	fmr	f0, f1

  111. 	fmr	f2, f1

  112. 	fmr	f3, f1

  113. 	fmr	f4, f1

  114. 	fmr	f5, f1

  115. 	fmr	f6, f1

  116. 	fmr	f7, f1

  117. 

  118. 	subi	N, N, 1

  119. 

  120. 	cmpwi	cr0, INCX, SIZE

  121. 	bne-	cr0, LL(100)

  122. 

  123. 	srawi.	r0, N, 4

  124. 	mtspr	CTR, r0

  125. 	beq-	cr0, LL(50)

  126. 

  127. 	LFD	f16,   0 * SIZE(X)

  128. 	LFD	f17,   1 * SIZE(X)

  129. 	LFD	f18,   2 * SIZE(X)

  130. 	LFD	f19,   3 * SIZE(X)

  131. 	LFD	f20,   4 * SIZE(X)

  132. 	LFD	f21,   5 * SIZE(X)

  133. 	LFD	f22,   6 * SIZE(X)

  134. 	LFD	f23,   7 * SIZE(X)

  135. 

  136. 	LFD	f24,   8 * SIZE(X)

  137. 	LFD	f25,   9 * SIZE(X)

  138. 	LFD	f26,  10 * SIZE(X)

  139. 	LFD	f27,  11 * SIZE(X)

  140. 	LFD	f28,  12 * SIZE(X)

  141. 	LFD	f29,  13 * SIZE(X)

  142. 	LFD	f30,  14 * SIZE(X)

  143. 	LFD	f31,  15 * SIZE(X)

  144. 

  145. 	fsub	f8,  f0,  f16

  146. 	fsub	f9,  f1,  f17

  147. 	fsub	f10, f2,  f18

  148. 	fsub	f11, f3,  f19

  149. 	fsub	f12, f4,  f20

  150. 	fsub	f13, f5,  f21

  151. 	fsub	f14, f6,  f22

  152. 	fsub	f15, f7,  f23

  153. 	bdz	LL(20)

  154. 	.align 4

  155. 

  156. LL(10):

  157. 	fsel	f0,  f8,  f0,  f16

  158. 	fsub	f8,  f0,  f24

  159. 	fsel	f1,  f9,  f1,  f17

  160. 	fsub	f9,  f1,  f25

  161. 	fsel	f2,  f10, f2,  f18

  162. 	fsub	f10, f2,  f26

  163. 	fsel	f3,  f11, f3,  f19

  164. 	fsub	f11, f3,  f27

  165. 

  166. 	LFD	f16,  16 * SIZE(X)

  167. 	LFD	f17,  17 * SIZE(X)

  168. 	LFD	f18,  18 * SIZE(X)

  169. 	LFD	f19,  19 * SIZE(X)

  170. 

  171. 	fsel	f4,  f12, f4,  f20

  172. 	fsub	f12, f4,  f28

  173. 	fsel	f5,  f13, f5,  f21

  174. 	fsub	f13, f5,  f29

  175. 	fsel	f6,  f14, f6,  f22

  176. 	fsub	f14, f6,  f30

  177. 	fsel	f7,  f15, f7,  f23

  178. 	fsub	f15, f7,  f31

  179. 

  180. 	LFD	f20,  20 * SIZE(X)

  181. 	LFD	f21,  21 * SIZE(X)

  182. 	LFD	f22,  22 * SIZE(X)

  183. 	LFD	f23,  23 * SIZE(X)

  184. 

  185. 	fsel	f0,  f8,  f0,  f24

  186. 	fsub	f8,  f0,  f16

  187. 	fsel	f1,  f9,  f1,  f25

  188. 	fsub	f9,  f1,  f17

  189. 	fsel	f2,  f10, f2,  f26

  190. 	fsub	f10, f2,  f18

  191. 	fsel	f3,  f11, f3,  f27

  192. 	fsub	f11, f3,  f19

  193. 

  194. 	LFD	f24,  24 * SIZE(X)

  195. 	LFD	f25,  25 * SIZE(X)

  196. 	LFD	f26,  26 * SIZE(X)

  197. 	LFD	f27,  27 * SIZE(X)

  198. 

  199. 	fsel	f4,  f12, f4,  f28

  200. 	fsub	f12, f4,  f20

  201. 	fsel	f5,  f13, f5,  f29

  202. 	fsub	f13, f5,  f21

  203. 	fsel	f6,  f14, f6,  f30

  204. 	fsub	f14, f6,  f22

  205. 	fsel	f7,  f15, f7,  f31

  206. 	fsub	f15, f7,  f23

  207. 

  208. 	LFD	f28,  28 * SIZE(X)

  209. 	LFD	f29,  29 * SIZE(X)

  210. 	LFD	f30,  30 * SIZE(X)

  211. 	LFD	f31,  31 * SIZE(X)

  212. 

  213. #ifndef POWER6

  214. 	L1_PREFETCH	X, PREA

  215. #endif

  216. 	addi	X, X, 16 * SIZE

  217. #ifdef POWER6

  218. 	L1_PREFETCH	X, PREA

  219. #endif

  220. 

  221. 	bdnz	LL(10)

  222. 	.align 4

  223. 

  224. LL(20):

  225. 	fsel	f0,  f8,  f0,  f16

  226. 	fsub	f8,  f0,  f24

  227. 	fsel	f1,  f9,  f1,  f17

  228. 	fsub	f9,  f1,  f25

  229. 	fsel	f2,  f10, f2,  f18

  230. 	fsub	f10, f2,  f26

  231. 	fsel	f3,  f11, f3,  f19

  232. 	fsub	f11, f3,  f27

  233. 

  234. 	fsel	f4,  f12, f4,  f20

  235. 	fsub	f12, f4,  f28

  236. 	fsel	f5,  f13, f5,  f21

  237. 	fsub	f13, f5,  f29

  238. 	fsel	f6,  f14, f6,  f22

  239. 	fsub	f14, f6,  f30

  240. 	fsel	f7,  f15, f7,  f23

  241. 	fsub	f15, f7,  f31

  242. 

  243. 	fsel	f0,  f8,  f0,  f24

  244. 	fsel	f1,  f9,  f1,  f25

  245. 	fsel	f2,  f10, f2,  f26

  246. 	fsel	f3,  f11, f3,  f27

  247. 	fsel	f4,  f12, f4,  f28

  248. 	fsel	f5,  f13, f5,  f29

  249. 	fsel	f6,  f14, f6,  f30

  250. 	fsel	f7,  f15, f7,  f31

  251. 

  252. 	addi	X, X, 16 * SIZE

  253. 	.align 4

  254. 

  255. LL(50):

  256. 	andi.	r0,  N, 15

  257. 	mtspr	CTR, r0

  258. 	beq	LL(999)

  259. 	.align 4

  260. 

  261. LL(60):

  262. 	LFD	f8,  0 * SIZE(X)

  263. 	addi	X, X,  1 * SIZE

  264. 	fsub	f16, f1, f8

  265. 	fsel	f1, f16, f1, f8

  266. 	bdnz	LL(60)

  267. 	b	LL(999)

  268. 	.align 4

  269. 

  270. LL(100):

  271. 	sub	X, X, INCX

  272. 

  273. 	srawi.	r0, N, 4

  274. 	mtspr	CTR,  r0

  275. 	beq-	LL(150)

  276. 

  277. 	LFDUX	f16,   X, INCX

  278. 	LFDUX	f17,   X, INCX

  279. 	LFDUX	f18,   X, INCX

  280. 	LFDUX	f19,   X, INCX

  281. 	LFDUX	f20,   X, INCX

  282. 	LFDUX	f21,   X, INCX

  283. 	LFDUX	f22,   X, INCX

  284. 	LFDUX	f23,   X, INCX

  285. 

  286. 	LFDUX	f24,   X, INCX

  287. 	LFDUX	f25,   X, INCX

  288. 	LFDUX	f26,   X, INCX

  289. 	LFDUX	f27,   X, INCX

  290. 	LFDUX	f28,   X, INCX

  291. 	LFDUX	f29,   X, INCX

  292. 	LFDUX	f30,   X, INCX

  293. 	LFDUX	f31,   X, INCX

  294. 

  295. 	fsub	f8,  f0,  f16

  296. 	fsub	f9,  f1,  f17

  297. 	fsub	f10, f2,  f18

  298. 	fsub	f11, f3,  f19

  299. 	fsub	f12, f4,  f20

  300. 	fsub	f13, f5,  f21

  301. 	fsub	f14, f6,  f22

  302. 	fsub	f15, f7,  f23

  303. 	bdz	LL(120)

  304. 	.align 4

  305. 

  306. LL(110):

  307. 	fsel	f0,  f8,  f0,  f16

  308. 	fsub	f8,  f0,  f24

  309. 	fsel	f1,  f9,  f1,  f17

  310. 	fsub	f9,  f1,  f25

  311. 	fsel	f2,  f10, f2,  f18

  312. 	fsub	f10, f2,  f26

  313. 	fsel	f3,  f11, f3,  f19

  314. 	fsub	f11, f3,  f27

  315. 

  316. 	LFDUX	f16,   X, INCX

  317. 	LFDUX	f17,   X, INCX

  318. 	LFDUX	f18,   X, INCX

  319. 	LFDUX	f19,   X, INCX

  320. 

  321. 	fsel	f4,  f12, f4,  f20

  322. 	fsub	f12, f4,  f28

  323. 	fsel	f5,  f13, f5,  f21

  324. 	fsub	f13, f5,  f29

  325. 	fsel	f6,  f14, f6,  f22

  326. 	fsub	f14, f6,  f30

  327. 	fsel	f7,  f15, f7,  f23

  328. 	fsub	f15, f7,  f31

  329. 

  330. 	LFDUX	f20,   X, INCX

  331. 	LFDUX	f21,   X, INCX

  332. 	LFDUX	f22,   X, INCX

  333. 	LFDUX	f23,   X, INCX

  334. 

  335. 	fsel	f0,  f8,  f0,  f24

  336. 	fsub	f8,  f0,  f16

  337. 	fsel	f1,  f9,  f1,  f25

  338. 	fsub	f9,  f1,  f17

  339. 	fsel	f2,  f10, f2,  f26

  340. 	fsub	f10, f2,  f18

  341. 	fsel	f3,  f11, f3,  f27

  342. 	fsub	f11, f3,  f19

  343. 

  344. 	LFDUX	f24,   X, INCX

  345. 	LFDUX	f25,   X, INCX

  346. 	LFDUX	f26,   X, INCX

  347. 	LFDUX	f27,   X, INCX

  348. 

  349. 	fsel	f4,  f12, f4,  f28

  350. 	fsub	f12, f4,  f20

  351. 	fsel	f5,  f13, f5,  f29

  352. 	fsub	f13, f5,  f21

  353. 	fsel	f6,  f14, f6,  f30

  354. 	fsub	f14, f6,  f22

  355. 	fsel	f7,  f15, f7,  f31

  356. 	fsub	f15, f7,  f23

  357. 

  358. 	LFDUX	f28,   X, INCX

  359. 	LFDUX	f29,   X, INCX

  360. 	LFDUX	f30,   X, INCX

  361. 	LFDUX	f31,   X, INCX

  362. 	bdnz	LL(110)

  363. 	.align 4

  364. 

  365. LL(120):

  366. 	fsel	f0,  f8,  f0,  f16

  367. 	fsub	f8,  f0,  f24

  368. 	fsel	f1,  f9,  f1,  f17

  369. 	fsub	f9,  f1,  f25

  370. 	fsel	f2,  f10, f2,  f18

  371. 	fsub	f10, f2,  f26

  372. 	fsel	f3,  f11, f3,  f19

  373. 	fsub	f11, f3,  f27

  374. 

  375. 	fsel	f4,  f12, f4,  f20

  376. 	fsub	f12, f4,  f28

  377. 	fsel	f5,  f13, f5,  f21

  378. 	fsub	f13, f5,  f29

  379. 	fsel	f6,  f14, f6,  f22

  380. 	fsub	f14, f6,  f30

  381. 	fsel	f7,  f15, f7,  f23

  382. 	fsub	f15, f7,  f31

  383. 

  384. 	fsel	f0,  f8,  f0,  f24

  385. 	fsel	f1,  f9,  f1,  f25

  386. 	fsel	f2,  f10, f2,  f26

  387. 	fsel	f3,  f11, f3,  f27

  388. 	fsel	f4,  f12, f4,  f28

  389. 	fsel	f5,  f13, f5,  f29

  390. 	fsel	f6,  f14, f6,  f30

  391. 	fsel	f7,  f15, f7,  f31

  392. 	.align 4

  393. 

  394. LL(150):

  395. 	andi.	r0,  N, 15

  396. 	mtspr	CTR, r0

  397. 	beq	LL(999)

  398. 	.align 4

  399. 

  400. LL(160):

  401. 	LFDUX	f8,    X, INCX

  402. 	fsub	f16, f1, f8

  403. 	fsel	f1, f16, f1, f8

  404. 	bdnz	LL(160)

  405. 	.align 4

  406. 

  407. LL(999):

  408. 	fsub	f8,  f0,  f1

  409. 	fsub	f9,  f2,  f3

  410. 	fsub	f10, f4,  f5

  411. 	fsub	f11, f6,  f7

  412. 

  413. 	fsel	f0,  f8,  f0,  f1

  414. 	fsel	f2,  f9,  f2,  f3

  415. 	fsel	f4,  f10, f4,  f5

  416. 	fsel	f6,  f11, f6,  f7

  417. 

  418. 	fsub	f8,  f0,  f2

  419. 	fsub	f9,  f4,  f6

  420. 	fsel	f0,  f8,  f0,  f2

  421. 	fsel	f4,  f9,  f4,  f6

  422. 

  423. 	fsub	f8,  f0,  f4

  424. 	fsel	f1,  f8,  f0,  f4

  425. 	.align 4

  426. 

  427. LL(1000):

  428. 	cmpwi	cr0, INCX, SIZE

  429. 	bne-	cr0, LL(1100)

  430. 

  431. 	srawi.	r0, NN, 3

  432. 	mtspr	CTR, r0

  433. 	beq-	cr0, LL(1050)

  434. 

  435. 	LFD	f8,   0 * SIZE(XX)

  436. 	LFD	f9,   1 * SIZE(XX)

  437. 	LFD	f10,  2 * SIZE(XX)

  438. 	LFD	f11,  3 * SIZE(XX)

  439. 	LFD	f12,  4 * SIZE(XX)

  440. 	LFD	f13,  5 * SIZE(XX)

  441. 	LFD	f14,  6 * SIZE(XX)

  442. 	LFD	f15,  7 * SIZE(XX)

  443. 	bdz	LL(1020)

  444. 	.align 4

  445. 

  446. LL(1010):

  447. 	addi	RET, RET, 1

  448. 	fcmpu	cr0, f1, f8

  449. 	beq	cr0, LL(9999)

  450. 

  451. 	addi	RET, RET, 1

  452. 	fcmpu	cr0, f1, f9

  453. 	beq	cr0, LL(9999)

  454. 

  455. 	addi	RET, RET, 1

  456. 	fcmpu	cr0, f1, f10

  457. 	beq	cr0, LL(9999)

  458. 

  459. 	addi	RET, RET, 1

  460. 	fcmpu	cr0, f1, f11

  461. 	beq	cr0, LL(9999)

  462. 

  463. 	LFD	f8,    8 * SIZE(XX)

  464. 	LFD	f9,    9 * SIZE(XX)

  465. 	LFD	f10,  10 * SIZE(XX)

  466. 	LFD	f11,  11 * SIZE(XX)

  467. 

  468. 	addi	RET, RET, 1

  469. 	fcmpu	cr0, f1, f12

  470. 	beq	cr0, LL(9999)

  471. 

  472. 	addi	RET, RET, 1

  473. 	fcmpu	cr0, f1, f13

  474. 	beq	cr0, LL(9999)

  475. 

  476. 	addi	RET, RET, 1

  477. 	fcmpu	cr0, f1, f14

  478. 	beq	cr0, LL(9999)

  479. 

  480. 	addi	RET, RET, 1

  481. 	fcmpu	cr0, f1, f15

  482. 	beq	cr0, LL(9999)

  483. 

  484. 	LFD	f12,  12 * SIZE(XX)

  485. 	LFD	f13,  13 * SIZE(XX)

  486. 	LFD	f14,  14 * SIZE(XX)

  487. 	LFD	f15,  15 * SIZE(XX)

  488. 

  489. 	addi	XX, XX,  8 * SIZE

  490. 	bdnz	LL(1010)

  491. 	.align 4

  492. 

  493. LL(1020):

  494. 	addi	XX, XX,  8 * SIZE

  495. 

  496. 	addi	RET, RET, 1

  497. 	fcmpu	cr0, f1, f8

  498. 	beq	cr0, LL(9999)

  499. 

  500. 	addi	RET, RET, 1

  501. 	fcmpu	cr0, f1, f9

  502. 	beq	cr0, LL(9999)

  503. 

  504. 	addi	RET, RET, 1

  505. 	fcmpu	cr0, f1, f10

  506. 	beq	cr0, LL(9999)

  507. 

  508. 	addi	RET, RET, 1

  509. 	fcmpu	cr0, f1, f11

  510. 	beq	cr0, LL(9999)

  511. 

  512. 	addi	RET, RET, 1

  513. 	fcmpu	cr0, f1, f12

  514. 	beq	cr0, LL(9999)

  515. 

  516. 	addi	RET, RET, 1

  517. 	fcmpu	cr0, f1, f13

  518. 	beq	cr0, LL(9999)

  519. 

  520. 	addi	RET, RET, 1

  521. 	fcmpu	cr0, f1, f14

  522. 	beq	cr0, LL(9999)

  523. 

  524. 	addi	RET, RET, 1

  525. 	fcmpu	cr0, f1, f15

  526. 	beq	cr0, LL(9999)

  527. 	.align 4

  528. 

  529. LL(1050):

  530. 	andi.	r0,  NN, 7

  531. 	mtspr	CTR, r0

  532. 	beq	LL(9999)

  533. 	.align 4

  534. 

  535. LL(1060):

  536. 	LFD	f8,  0 * SIZE(XX)

  537. 	addi	XX, XX,  1 * SIZE

  538. 	addi	RET, RET, 1

  539. 	fcmpu	cr0, f1, f8

  540. 	beq	cr0, LL(9999)

  541. 	bdnz	LL(1060)

  542. 	b	LL(9999)

  543. 	.align 4

  544. 

  545. LL(1100):

  546. 	sub	XX, XX, INCX

  547. 

  548. 	srawi.	r0, NN, 3

  549. 	mtspr	CTR,  r0

  550. 	beq-	LL(1150)

  551. 

  552. 	LFDUX	f8,   XX, INCX

  553. 	LFDUX	f9,   XX, INCX

  554. 	LFDUX	f10,   XX, INCX

  555. 	LFDUX	f11,   XX, INCX

  556. 	LFDUX	f12,   XX, INCX

  557. 	LFDUX	f13,   XX, INCX

  558. 	LFDUX	f14,   XX, INCX

  559. 	LFDUX	f15,   XX, INCX

  560. 	bdz	LL(1120)

  561. 	.align 4

  562. 

  563. LL(1110):

  564. 	addi	RET, RET, 1

  565. 	fcmpu	cr0, f1, f8

  566. 	beq	cr0, LL(9999)

  567. 

  568. 	addi	RET, RET, 1

  569. 	fcmpu	cr0, f1, f9

  570. 	beq	cr0, LL(9999)

  571. 

  572. 	addi	RET, RET, 1

  573. 	fcmpu	cr0, f1, f10

  574. 	beq	cr0, LL(9999)

  575. 

  576. 	addi	RET, RET, 1

  577. 	fcmpu	cr0, f1, f11

  578. 	beq	cr0, LL(9999)

  579. 

  580. 	LFDUX	f8,   XX, INCX

  581. 	LFDUX	f9,   XX, INCX

  582. 	LFDUX	f10,  XX, INCX

  583. 	LFDUX	f11,  XX, INCX

  584. 

  585. 	addi	RET, RET, 1

  586. 	fcmpu	cr0, f1, f12

  587. 	beq	cr0, LL(9999)

  588. 

  589. 	addi	RET, RET, 1

  590. 	fcmpu	cr0, f1, f13

  591. 	beq	cr0, LL(9999)

  592. 

  593. 	addi	RET, RET, 1

  594. 	fcmpu	cr0, f1, f14

  595. 	beq	cr0, LL(9999)

  596. 

  597. 	addi	RET, RET, 1

  598. 	fcmpu	cr0, f1, f15

  599. 	beq	cr0, LL(9999)

  600. 

  601. 	LFDUX	f12,  XX, INCX

  602. 	LFDUX	f13,  XX, INCX

  603. 	LFDUX	f14,  XX, INCX

  604. 	LFDUX	f15,  XX, INCX

  605. 

  606. 	bdnz	LL(1110)

  607. 	.align 4

  608. 

  609. LL(1120):

  610. 	addi	RET, RET, 1

  611. 	fcmpu	cr0, f1, f8

  612. 	beq	cr0, LL(9999)

  613. 

  614. 	addi	RET, RET, 1

  615. 	fcmpu	cr0, f1, f9

  616. 	beq	cr0, LL(9999)

  617. 

  618. 	addi	RET, RET, 1

  619. 	fcmpu	cr0, f1, f10

  620. 	beq	cr0, LL(9999)

  621. 

  622. 	addi	RET, RET, 1

  623. 	fcmpu	cr0, f1, f11

  624. 	beq	cr0, LL(9999)

  625. 

  626. 	addi	RET, RET, 1

  627. 	fcmpu	cr0, f1, f12

  628. 	beq	cr0, LL(9999)

  629. 

  630. 	addi	RET, RET, 1

  631. 	fcmpu	cr0, f1, f13

  632. 	beq	cr0, LL(9999)

  633. 

  634. 	addi	RET, RET, 1

  635. 	fcmpu	cr0, f1, f14

  636. 	beq	cr0, LL(9999)

  637. 

  638. 	addi	RET, RET, 1

  639. 	fcmpu	cr0, f1, f15

  640. 	beq	cr0, LL(9999)

  641. 	.align 4

  642. 

  643. LL(1150):

  644. 	andi.	r0,  NN, 7

  645. 	mtspr	CTR, r0

  646. 	beq	LL(9999)

  647. 	.align 4

  648. 

  649. LL(1160):

  650. 	LFDUX	f8,    XX, INCX

  651. 	addi	RET, RET, 1

  652. 	fcmpu	cr0, f1, f8

  653. 	beq	cr0, LL(9999)

  654. 	bdnz	LL(1160)

  655. 	.align 4

  656. 

  657. LL(9999):

  658. 	lfd	f14,    0(SP)

  659. 	lfd	f15,    8(SP)

  660. 	lfd	f16,   16(SP)

  661. 	lfd	f17,   24(SP)

  662. 

  663. 	lfd	f18,   32(SP)

  664. 	lfd	f19,   40(SP)

  665. 	lfd	f20,   48(SP)

  666. 	lfd	f21,   56(SP)

  667. 

  668. 	lfd	f22,   64(SP)

  669. 	lfd	f23,   72(SP)

  670. 	lfd	f24,   80(SP)

  671. 	lfd	f25,   88(SP)

  672. 

  673. 	lfd	f26,   96(SP)

  674. 	lfd	f27,  104(SP)

  675. 	lfd	f28,  112(SP)

  676. 	lfd	f29,  120(SP)

  677. 

  678. 	lfd	f30,  128(SP)

  679. 	lfd	f31,  136(SP)

  680. 

  681. 	addi	SP, SP, STACKSIZE

  682. 	blr

  683. 

  684. 	EPILOGUE