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OpenBLAS/kernel/power/iamin_hummer.S

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  1. /*********************************************************************/

  2. /* Copyright 2009, 2010 The University of Texas at Austin.           */

  3. /* All rights reserved.                                              */

  4. /*                                                                   */

  5. /* Redistribution and use in source and binary forms, with or        */

  6. /* without modification, are permitted provided that the following   */

  7. /* conditions are met:                                               */

  8. /*                                                                   */

  9. /*   1. Redistributions of source code must retain the above         */

  10. /*      copyright notice, this list of conditions and the following  */

  11. /*      disclaimer.                                                  */

  12. /*                                                                   */

  13. /*   2. Redistributions in binary form must reproduce the above      */

  14. /*      copyright notice, this list of conditions and the following  */

  15. /*      disclaimer in the documentation and/or other materials       */

  16. /*      provided with the distribution.                              */

  17. /*                                                                   */

  18. /*    THIS  SOFTWARE IS PROVIDED  BY THE  UNIVERSITY OF  TEXAS AT    */

  19. /*    AUSTIN  ``AS IS''  AND ANY  EXPRESS OR  IMPLIED WARRANTIES,    */

  20. /*    INCLUDING, BUT  NOT LIMITED  TO, THE IMPLIED  WARRANTIES OF    */

  21. /*    MERCHANTABILITY  AND FITNESS FOR  A PARTICULAR  PURPOSE ARE    */

  22. /*    DISCLAIMED.  IN  NO EVENT SHALL THE UNIVERSITY  OF TEXAS AT    */

  23. /*    AUSTIN OR CONTRIBUTORS BE  LIABLE FOR ANY DIRECT, INDIRECT,    */

  24. /*    INCIDENTAL,  SPECIAL, EXEMPLARY,  OR  CONSEQUENTIAL DAMAGES    */

  25. /*    (INCLUDING, BUT  NOT LIMITED TO,  PROCUREMENT OF SUBSTITUTE    */

  26. /*    GOODS  OR  SERVICES; LOSS  OF  USE,  DATA,  OR PROFITS;  OR    */

  27. /*    BUSINESS INTERRUPTION) HOWEVER CAUSED  AND ON ANY THEORY OF    */

  28. /*    LIABILITY, WHETHER  IN CONTRACT, STRICT  LIABILITY, OR TORT    */

  29. /*    (INCLUDING NEGLIGENCE OR OTHERWISE)  ARISING IN ANY WAY OUT    */

  30. /*    OF  THE  USE OF  THIS  SOFTWARE,  EVEN  IF ADVISED  OF  THE    */

  31. /*    POSSIBILITY OF SUCH DAMAGE.                                    */

  32. /*                                                                   */

  33. /* The views and conclusions contained in the software and           */

  34. /* documentation are those of the authors and should not be          */

  35. /* interpreted as representing official policies, either expressed   */

  36. /* or implied, of The University of Texas at Austin.                 */

  37. /*********************************************************************/

  38. 

  39. #define ASSEMBLER

  40. #include "common.h"

  41. 

  42. #define N	r3

  43. #define X	r4

  44. #define INCX	r5

  45. 

  46. #define INCX2	r6

  47. #define X2	r7

  48. 

  49. #define	XX	r8

  50. #define RET	r9

  51. #define NN	r10

  52. 

  53. #define C1	f1

  54. #define C2	f0

  55. #define C3	f2

  56. #define C4	f3

  57. 

  58. #define A1	f4

  59. #define A2	f5

  60. #define A3	f6

  61. #define A4	f7

  62. #define A5	f8

  63. #define A6	f9

  64. #define A7	f10

  65. #define A8	f11

  66. 

  67. #define F1	f12

  68. #define F2	f13

  69. #define F3	f14

  70. #define F4	f15

  71. #define F5	f16

  72. #define F6	f17

  73. #define F7	f18

  74. #define F8	f19

  75. 

  76. #define T1	f20

  77. #define T2	f21

  78. #define T3	f22

  79. #define T4	f23

  80. #define T5	f24

  81. #define T6	f25

  82. #define T7	f26

  83. #define T8	f27

  84. 

  85. 

  86. 	PROLOGUE

  87. 	PROFCODE

  88. 

  89. 	li	r10, -16

  90. 

  91. 	stfpdux	f14, SP, r10

  92. 	stfpdux	f15, SP, r10

  93. 

  94. 	stfpdux	f16, SP, r10

  95. 	stfpdux	f17, SP, r10

  96. 	stfpdux	f18, SP, r10

  97. 	stfpdux	f19, SP, r10

  98. 

  99. 	stfpdux	f20, SP, r10

  100. 	stfpdux	f21, SP, r10

  101. 	stfpdux	f22, SP, r10

  102. 	stfpdux	f23, SP, r10

  103. 

  104. 	stfpdux	f24, SP, r10

  105. 	stfpdux	f25, SP, r10

  106. 	stfpdux	f26, SP, r10

  107. 	stfpdux	f27, SP, r10

  108. 

  109. 

  110. #ifdef F_INTERFACE

  111. 	LDINT	N,    0(N)

  112. 	LDINT	INCX, 0(INCX)

  113. #endif

  114. 

  115. 	slwi	INCX,  INCX, BASE_SHIFT

  116. 	add	INCX2, INCX, INCX

  117. 

  118. 	li	RET, 0

  119. 	cmpwi	cr0, N, 0

  120. 	ble	LL(999)

  121. 	mr	NN, N

  122. 	cmpwi	cr0, INCX, 0

  123. 	ble	LL(999)

  124. 

  125. 	LFD	C1, 0 * SIZE(X)

  126. 

  127. 	addi	N, N, -1

  128. 	cmpwi	cr0, N, 0

  129. 	li	RET, 1

  130. 	fabs	C1, C1

  131. 	ble	LL(999)

  132. 

  133. 	fsmfp	C1, C1

  134. 	mr	XX, X

  135. 	fpmr	C2, C1

  136. 	add	X, X, INCX

  137. 	fpmr	C3, C1

  138. 	fpmr	C4, C1

  139. 

  140. 	cmpwi	cr0, INCX, SIZE

  141. 	bne	LL(100)

  142. 

  143. 	andi.	r0, X, 2 * SIZE - 1

  144. 	beq	LL(05)

  145. 

  146. 	LFD	C2, 0 * SIZE(X)

  147. 	add	X, X, INCX

  148. 

  149. 	addi	N, N, -1

  150. 	cmpwi	cr0, N, 0

  151. 	fabs	C2, C2

  152. 	ble	LL(20)

  153. 	.align 4

  154. 

  155. LL(05):

  156. 	sub	X, X, INCX2

  157. 

  158. 	srawi.	r0, N, 4

  159. 	mtspr	CTR,  r0

  160. 	beq-	LL(15)

  161. 

  162. 	LFPDUX	A1,    X, INCX2

  163. 	LFPDUX	A2,    X, INCX2

  164. 	LFPDUX	A3,    X, INCX2

  165. 	LFPDUX	A4,    X, INCX2

  166. 

  167. 	LFPDUX	A5,    X, INCX2

  168. 	fpabs	T1, A1

  169. 	LFPDUX	A6,    X, INCX2

  170. 	fpabs	T2, A2

  171. 	LFPDUX	A7,    X, INCX2

  172. 	fpabs	T3, A3

  173. 	LFPDUX	A8,    X, INCX2

  174. 	fpabs	T4, A4

  175. 	bdz	LL(13)

  176. 	.align 4

  177. 

  178. LL(12):

  179. 	fpsub	F1, T1, C1

  180. 	LFPDUX	A1,    X, INCX2

  181. 	fpsub	F2, T2, C2

  182. 	LFPDUX	A2,    X, INCX2

  183. 	fpsub	F3, T3, C3

  184. 	LFPDUX	A3,    X, INCX2

  185. 	fpsub	F4, T4, C4

  186. 	LFPDUX	A4,    X, INCX2

  187. 

  188. 	fpabs	T5, A5

  189. 	fpabs	T6, A6

  190. 	fpabs	T7, A7

  191. 	fpabs	T8, A8

  192. 

  193. 	fpsel	C1, F1, C1, T1

  194. 	LFPDUX	A5,    X, INCX2

  195. 	fpsel	C2, F2, C2, T2

  196. 	LFPDUX	A6,    X, INCX2

  197. 	fpsel	C3, F3, C3, T3

  198. 	LFPDUX	A7,    X, INCX2

  199. 	fpsel	C4, F4, C4, T4

  200. 	LFPDUX	A8,    X, INCX2

  201. 

  202. 	fpsub	F5, T5, C1

  203. 	fpsub	F6, T6, C2

  204. 	fpsub	F7, T7, C3

  205. 	fpsub	F8, T8, C4

  206. 

  207. 	fpabs	T1, A1

  208. 	fpabs	T2, A2

  209. 	fpabs	T3, A3

  210. 	fpabs	T4, A4

  211. 

  212. 	fpsel	C1, F5, C1, T5

  213. 	fpsel	C2, F6, C2, T6

  214. 	fpsel	C3, F7, C3, T7

  215. 	fpsel	C4, F8, C4, T8

  216. 	bdnz	LL(12)

  217. 	.align 4

  218. 

  219. LL(13):

  220. 	fpabs	T5, A5

  221. 	fpabs	T6, A6

  222. 	fpabs	T7, A7

  223. 	fpabs	T8, A8

  224. 

  225. 	fpsub	F1, T1, C1

  226. 	fpsub	F2, T2, C2

  227. 	fpsub	F3, T3, C3

  228. 	fpsub	F4, T4, C4

  229. 

  230. 	fpsel	C1, F1, C1, T1

  231. 	fpsel	C2, F2, C2, T2

  232. 	fpsel	C3, F3, C3, T3

  233. 	fpsel	C4, F4, C4, T4

  234. 

  235. 	fpsub	F5, T5, C1

  236. 	fpsub	F6, T6, C2

  237. 	fpsub	F7, T7, C3

  238. 	fpsub	F8, T8, C4

  239. 

  240. 	fpsel	C1, F5, C1, T5

  241. 	fpsel	C2, F6, C2, T6

  242. 	fpsel	C3, F7, C3, T7

  243. 	fpsel	C4, F8, C4, T8

  244. 	.align 4

  245. 

  246. LL(15):

  247. 	andi.	r0,  N, 15

  248. 	beq	LL(20)

  249. 

  250. 	andi.	r0,  N, 8

  251. 	beq	LL(16)

  252. 

  253. 	LFPDUX	A1,    X, INCX2

  254. 	LFPDUX	A2,    X, INCX2

  255. 	LFPDUX	A3,    X, INCX2

  256. 	LFPDUX	A4,    X, INCX2

  257. 

  258. 	fpabs	A1, A1

  259. 	fpabs	A2, A2

  260. 	fpabs	A3, A3

  261. 	fpabs	A4, A4

  262. 

  263. 	fpsub	F1, A1, C1

  264. 	fpsub	F2, A2, C2

  265. 	fpsub	F3, A3, C3

  266. 	fpsub	F4, A4, C4

  267. 

  268. 	fpsel	C1, F1, C1, A1

  269. 	fpsel	C2, F2, C2, A2

  270. 	fpsel	C3, F3, C3, A3

  271. 	fpsel	C4, F4, C4, A4

  272. 	.align 4

  273. 

  274. LL(16):

  275. 	andi.	r0,  N, 4

  276. 	beq	LL(17)

  277. 

  278. 	LFPDUX	A1,    X, INCX2

  279. 	LFPDUX	A2,    X, INCX2

  280. 

  281. 	fpabs	A1, A1

  282. 	fpabs	A2, A2

  283. 

  284. 	fpsub	F1, A1, C1

  285. 	fpsub	F2, A2, C2

  286. 

  287. 	fpsel	C1, F1, C1, A1

  288. 	fpsel	C2, F2, C2, A2

  289. 	.align 4

  290. 

  291. LL(17):

  292. 	andi.	r0,  N, 2

  293. 	beq	LL(18)

  294. 

  295. 	LFPDUX	A1,    X, INCX2

  296. 	fpabs	A1, A1

  297. 	fpsub	F1, A1, C1

  298. 	fpsel	C1, F1, C1, A1

  299. 	.align 4

  300. 

  301. LL(18):

  302. 	andi.	r0,  N, 1

  303. 	beq	LL(20)

  304. 

  305. 	LFDUX	A1,    X, INCX2

  306. 	fabs	A1, A1

  307. 	fsub	F1, A1, C1

  308. 	fsel	C1, F1, C1, A1

  309. 	.align 4

  310. 

  311. LL(20):

  312. 	fpsub	F1,  C2, C1

  313. 	fpsub	F2,  C4, C3

  314. 

  315. 	fpsel	C1,  F1,  C1,  C2

  316. 	fpsel	C3,  F2,  C3,  C4

  317. 

  318. 	fpsub	F1,  C3, C1

  319. 	fpsel	C1,  F1,  C1,  C3

  320. 

  321. 	fsmtp	C2, C1

  322. 

  323. 	fsub	F1,  C2, C1

  324. 	fsel	C1,  F1,  C1,  C2

  325.  	li	RET, 0

  326. 

  327. 	fsmfp	C1, C1

  328. 	andi.	r0, XX, 2 * SIZE - 1

  329. 	beq	LL(21)

  330. 

  331. 	LFD	A1, 0 * SIZE(XX)

  332. 	add	XX, XX, INCX

  333. 

  334. 	addi	NN, NN, -1

  335.  	addi	RET, RET, 1

  336. 

  337. 	fabs	A1, A1

  338. 	fcmpu	cr0, C1, A1

  339. 	beq	cr0, LL(999)

  340. 	.align 4

  341. 

  342. LL(21):

  343. 	sub	XX, XX, INCX2

  344. 

  345. 	srawi.	r0, NN, 4

  346. 	mtspr	CTR,  r0

  347. 	beq-	LL(25)

  348. 

  349. 	LFPDUX	A1,    XX, INCX2

  350. 	LFPDUX	A2,    XX, INCX2

  351. 	LFPDUX	A3,    XX, INCX2

  352. 	LFPDUX	A4,    XX, INCX2

  353. 

  354. 	LFPDUX	A5,    XX, INCX2

  355. 	LFPDUX	A6,    XX, INCX2

  356. 	LFPDUX	A7,    XX, INCX2

  357. 	LFPDUX	A8,    XX, INCX2

  358. 

  359. 	fpabs	T1, A1

  360. 	fpabs	T2, A2

  361. 	fpabs	T3, A3

  362. 	fpabs	T4, A4

  363. 

  364. 	fpabs	T5, A5

  365. 	fpabs	T6, A6

  366. 	fpabs	T7, A7

  367. 	fpabs	T8, A8

  368. 

  369. 	bdz	LL(23)

  370. 	.align 4

  371. 

  372. LL(22):

  373. 	addi	RET, RET, 1

  374. 	fcmpu	cr0, C1, T1

  375. 	LFPDUX	A1,    XX, INCX2

  376. 	beq	cr0, LL(999)

  377. 

  378. 	addi	RET, RET, 1

  379. 	fscmp	cr0, C1, T1

  380. 	LFPDUX	A2,    XX, INCX2

  381. 	beq	cr0, LL(999)

  382. 

  383. 	addi	RET, RET, 1

  384. 	fcmpu	cr0, C1, T2

  385. 	LFPDUX	A3,    XX, INCX2

  386. 	beq	cr0, LL(999)

  387. 

  388. 	addi	RET, RET, 1

  389. 	fscmp	cr0, C1, T2

  390. 	LFPDUX	A4,    XX, INCX2

  391. 	beq	cr0, LL(999)

  392. 

  393. 	addi	RET, RET, 1

  394. 	fcmpu	cr0, C1, T3

  395. 	LFPDUX	A5,    XX, INCX2

  396. 	beq	cr0, LL(999)

  397. 

  398. 	addi	RET, RET, 1

  399. 	fscmp	cr0, C1, T3

  400.  	LFPDUX	A6,    XX, INCX2

  401. 	beq	cr0, LL(999)

  402. 

  403. 	addi	RET, RET, 1

  404. 	fcmpu	cr0, C1, T4

  405. 	LFPDUX	A7,    XX, INCX2

  406. 	beq	cr0, LL(999)

  407. 

  408. 	addi	RET, RET, 1

  409. 	fscmp	cr0, C1, T4

  410. 	LFPDUX	A8,    XX, INCX2

  411. 	beq	cr0, LL(999)

  412. 

  413. 	addi	RET, RET, 1

  414. 	fcmpu	cr0, C1, T5

  415. 	fpabs	T1, A1

  416. 	beq	cr0, LL(999)

  417. 

  418. 	addi	RET, RET, 1

  419. 	fscmp	cr0, C1, T5

  420. 	fpabs	T2, A2

  421. 	beq	cr0, LL(999)

  422. 

  423. 	addi	RET, RET, 1

  424. 	fcmpu	cr0, C1, T6

  425. 	fpabs	T3, A3

  426. 	beq	cr0, LL(999)

  427. 

  428. 	addi	RET, RET, 1

  429. 	fscmp	cr0, C1, T6

  430. 	fpabs	T4, A4

  431. 	beq	cr0, LL(999)

  432. 

  433. 	addi	RET, RET, 1

  434. 	fcmpu	cr0, C1, T7

  435. 	fpabs	T5, A5

  436. 	beq	cr0, LL(999)

  437. 

  438. 	addi	RET, RET, 1

  439. 	fscmp	cr0, C1, T7

  440. 	fpabs	T6, A6

  441. 	beq	cr0, LL(999)

  442. 

  443. 	addi	RET, RET, 1

  444. 	fcmpu	cr0, C1, T8

  445. 	fpabs	T7, A7

  446. 	beq	cr0, LL(999)

  447. 

  448. 	addi	RET, RET, 1

  449. 	fscmp	cr0, C1, T8

  450. 	fpabs	T8, A8

  451. 	beq	cr0, LL(999)

  452. 	bdnz	LL(22)

  453. 	.align 4

  454. 

  455. LL(23):

  456. 	addi	RET, RET, 1

  457. 	fcmpu	cr0, C1, T1

  458. 	beq	cr0, LL(999)

  459. 

  460. 	addi	RET, RET, 1

  461. 	fscmp	cr0, C1, T1

  462. 	beq	cr0, LL(999)

  463. 

  464. 	addi	RET, RET, 1

  465. 	fcmpu	cr0, C1, T2

  466. 	beq	cr0, LL(999)

  467. 

  468. 	addi	RET, RET, 1

  469. 	fscmp	cr0, C1, T2

  470. 	beq	cr0, LL(999)

  471. 

  472. 	addi	RET, RET, 1

  473. 	fcmpu	cr0, C1, T3

  474. 	beq	cr0, LL(999)

  475. 

  476. 	addi	RET, RET, 1

  477. 	fscmp	cr0, C1, T3

  478. 	beq	cr0, LL(999)

  479. 

  480. 	addi	RET, RET, 1

  481. 	fcmpu	cr0, C1, T4

  482. 	beq	cr0, LL(999)

  483. 

  484. 	addi	RET, RET, 1

  485. 	fscmp	cr0, C1, T4

  486. 	beq	cr0, LL(999)

  487. 

  488. 	addi	RET, RET, 1

  489. 	fcmpu	cr0, C1, T5

  490. 	beq	cr0, LL(999)

  491. 

  492. 	addi	RET, RET, 1

  493. 	fscmp	cr0, C1, T5

  494. 	beq	cr0, LL(999)

  495. 

  496. 	addi	RET, RET, 1

  497. 	fcmpu	cr0, C1, T6

  498. 	beq	cr0, LL(999)

  499. 

  500. 	addi	RET, RET, 1

  501. 	fscmp	cr0, C1, T6

  502. 	beq	cr0, LL(999)

  503. 

  504. 	addi	RET, RET, 1

  505. 	fcmpu	cr0, C1, T7

  506. 	beq	cr0, LL(999)

  507. 

  508. 	addi	RET, RET, 1

  509. 	fscmp	cr0, C1, T7

  510. 	beq	cr0, LL(999)

  511. 

  512. 	addi	RET, RET, 1

  513. 	fcmpu	cr0, C1, T8

  514. 	beq	cr0, LL(999)

  515. 

  516. 	addi	RET, RET, 1

  517. 	fscmp	cr0, C1, T8

  518. 	beq	cr0, LL(999)

  519. 	.align 4

  520. 

  521. LL(25):

  522. 	andi.	r0,  NN, 8

  523. 	beq	LL(26)

  524. 

  525. 	LFPDUX	A1,    XX, INCX2

  526. 	LFPDUX	A2,    XX, INCX2

  527. 	LFPDUX	A3,    XX, INCX2

  528. 	LFPDUX	A4,    XX, INCX2

  529. 

  530. 	fpabs	T1, A1

  531. 	fpabs	T2, A2

  532. 	fpabs	T3, A3

  533. 	fpabs	T4, A4

  534. 

  535. 	addi	RET, RET, 1

  536. 	fcmpu	cr0, C1, T1

  537. 	beq	cr0, LL(999)

  538. 

  539. 	addi	RET, RET, 1

  540. 	fscmp	cr0, C1, T1

  541. 	beq	cr0, LL(999)

  542. 

  543. 	addi	RET, RET, 1

  544. 	fcmpu	cr0, C1, T2

  545. 	beq	cr0, LL(999)

  546. 

  547. 	addi	RET, RET, 1

  548. 	fscmp	cr0, C1, T2

  549. 	beq	cr0, LL(999)

  550. 

  551. 	addi	RET, RET, 1

  552. 	fcmpu	cr0, C1, T3

  553. 	beq	cr0, LL(999)

  554. 

  555. 	addi	RET, RET, 1

  556. 	fscmp	cr0, C1, T3

  557. 	beq	cr0, LL(999)

  558. 

  559. 	addi	RET, RET, 1

  560. 	fcmpu	cr0, C1, T4

  561. 	beq	cr0, LL(999)

  562. 

  563. 	addi	RET, RET, 1

  564. 	fscmp	cr0, C1, T4

  565. 	beq	cr0, LL(999)

  566. 	.align 4

  567. 

  568. LL(26):

  569. 	andi.	r0,  NN, 4

  570. 	beq	LL(27)

  571. 

  572. 	LFPDUX	A1,    XX, INCX2

  573. 	LFPDUX	A2,    XX, INCX2

  574. 

  575. 	fpabs	T1, A1

  576. 	fpabs	T2, A2

  577. 

  578. 	addi	RET, RET, 1

  579. 	fcmpu	cr0, C1, T1

  580. 	beq	cr0, LL(999)

  581. 

  582. 	addi	RET, RET, 1

  583. 	fscmp	cr0, C1, T1

  584. 	beq	cr0, LL(999)

  585. 

  586. 	addi	RET, RET, 1

  587. 	fcmpu	cr0, C1, T2

  588. 	beq	cr0, LL(999)

  589. 

  590. 	addi	RET, RET, 1

  591. 	fscmp	cr0, C1, T2

  592. 	beq	cr0, LL(999)

  593. 	.align 4

  594. 

  595. LL(27):

  596. 	andi.	r0,  NN, 2

  597. 	beq	LL(28)

  598. 

  599. 	LFPDUX	A1,    XX, INCX2

  600. 

  601. 	fpabs	T1, A1

  602. 

  603. 	addi	RET, RET, 1

  604. 	fcmpu	cr0, C1, T1

  605. 	beq	cr0, LL(999)

  606. 

  607. 	addi	RET, RET, 1

  608. 	fscmp	cr0, C1, T1

  609. 	beq	cr0, LL(999)

  610. 	.align 4

  611. 

  612. LL(28):

  613. 	andi.	r0,  NN, 1

  614. 	beq	LL(999)

  615. 	addi	RET, RET, 1

  616. 	b	LL(999)

  617. 	.align 4

  618. 

  619. LL(100):

  620. 	sub	X, X, INCX

  621. 

  622. 	srawi.	r0, N, 4

  623. 	mtspr	CTR,  r0

  624. 	beq-	LL(105)

  625. 

  626. 	LFDUX	A1,    X, INCX

  627. 	LFDUX	A2,    X, INCX

  628. 	LFDUX	A3,    X, INCX

  629. 	LFDUX	A4,    X, INCX

  630. 	LFSDUX	A1,    X, INCX

  631. 	LFSDUX	A2,    X, INCX

  632. 	LFSDUX	A3,    X, INCX

  633. 	LFSDUX	A4,    X, INCX

  634. 

  635. 	LFDUX	A5,    X, INCX

  636. 	LFDUX	A6,    X, INCX

  637. 	LFDUX	A7,    X, INCX

  638. 	LFDUX	A8,    X, INCX

  639. 	LFSDUX	A5,    X, INCX

  640. 	fpabs	T1, A1

  641. 	LFSDUX	A6,    X, INCX

  642. 	fpabs	T2, A2

  643. 	LFSDUX	A7,    X, INCX

  644. 	fpabs	T3, A3

  645. 	LFSDUX	A8,    X, INCX

  646. 	fpabs	T4, A4

  647. 	bdz	LL(103)

  648. 	.align 4

  649. 

  650. LL(102):

  651. 	fpsub	F1, T1, C1

  652. 	LFDUX	A1,    X, INCX

  653. 	fpsub	F2, T2, C2

  654. 	LFDUX	A2,    X, INCX

  655. 	fpsub	F3, T3, C3

  656. 	LFDUX	A3,    X, INCX

  657. 	fpsub	F4, T4, C4

  658. 	LFDUX	A4,    X, INCX

  659. 

  660. 	fpabs	T5, A5

  661. 	LFSDUX	A1,    X, INCX

  662. 	fpabs	T6, A6

  663. 	LFSDUX	A2,    X, INCX

  664. 	fpabs	T7, A7

  665. 	LFSDUX	A3,    X, INCX

  666. 	fpabs	T8, A8

  667. 	LFSDUX	A4,    X, INCX

  668. 

  669. 	fpsel	C1, F1, C1, T1

  670. 	LFDUX	A5,    X, INCX

  671. 	fpsel	C2, F2, C2, T2

  672. 	LFDUX	A6,    X, INCX

  673. 	fpsel	C3, F3, C3, T3

  674. 	LFDUX	A7,    X, INCX

  675. 	fpsel	C4, F4, C4, T4

  676. 	LFDUX	A8,    X, INCX

  677. 

  678. 	fpsub	F5, T5, C1

  679. 	LFSDUX	A5,    X, INCX

  680. 	fpsub	F6, T6, C2

  681. 	LFSDUX	A6,    X, INCX

  682. 	fpsub	F7, T7, C3

  683. 	LFSDUX	A7,    X, INCX

  684. 	fpsub	F8, T8, C4

  685. 	LFSDUX	A8,    X, INCX

  686. 

  687. 	fpabs	T1, A1

  688. 	fpabs	T2, A2

  689. 	fpabs	T3, A3

  690. 	fpabs	T4, A4

  691. 

  692. 	fpsel	C1, F5, C1, T5

  693. 	fpsel	C2, F6, C2, T6

  694. 	fpsel	C3, F7, C3, T7

  695. 	fpsel	C4, F8, C4, T8

  696. 	bdnz	LL(102)

  697. 	.align 4

  698. 

  699. LL(103):

  700. 	fpabs	T5, A5

  701. 	fpabs	T6, A6

  702. 	fpabs	T7, A7

  703. 	fpabs	T8, A8

  704. 

  705. 	fpsub	F1, T1, C1

  706. 	fpsub	F2, T2, C2

  707. 	fpsub	F3, T3, C3

  708. 	fpsub	F4, T4, C4

  709. 

  710. 	fpsel	C1, F1, C1, T1

  711. 	fpsel	C2, F2, C2, T2

  712. 	fpsel	C3, F3, C3, T3

  713. 	fpsel	C4, F4, C4, T4

  714. 

  715. 	fpsub	F5, T5, C1

  716. 	fpsub	F6, T6, C2

  717. 	fpsub	F7, T7, C3

  718. 	fpsub	F8, T8, C4

  719. 

  720. 	fpsel	C1, F5, C1, T5

  721. 	fpsel	C2, F6, C2, T6

  722. 	fpsel	C3, F7, C3, T7

  723. 	fpsel	C4, F8, C4, T8

  724. 	.align 4

  725. 

  726. LL(105):

  727. 	andi.	r0,  N, 15

  728. 	beq	LL(120)

  729. 

  730. 	andi.	r0,  N, 8

  731. 	beq	LL(106)

  732. 

  733. 	LFDUX	A1,    X, INCX

  734. 	LFDUX	A2,    X, INCX

  735. 	LFDUX	A3,    X, INCX

  736. 	LFDUX	A4,    X, INCX

  737. 	LFSDUX	A1,    X, INCX

  738. 	LFSDUX	A2,    X, INCX

  739. 	LFSDUX	A3,    X, INCX

  740. 	LFSDUX	A4,    X, INCX

  741. 

  742. 	fpabs	A1, A1

  743. 	fpabs	A2, A2

  744. 	fpabs	A3, A3

  745. 	fpabs	A4, A4

  746. 

  747. 	fpsub	F1, A1, C1

  748. 	fpsub	F2, A2, C2

  749. 	fpsub	F3, A3, C3

  750. 	fpsub	F4, A4, C4

  751. 

  752. 	fpsel	C1, F1, C1, A1

  753. 	fpsel	C2, F2, C2, A2

  754. 	fpsel	C3, F3, C3, A3

  755. 	fpsel	C4, F4, C4, A4

  756. 	.align 4

  757. 

  758. LL(106):

  759. 	andi.	r0,  N, 4

  760. 	beq	LL(107)

  761. 

  762. 	LFDUX	A1,    X, INCX

  763. 	LFDUX	A2,    X, INCX

  764. 	LFDUX	A3,    X, INCX

  765. 	LFDUX	A4,    X, INCX

  766. 

  767. 	fabs	A1, A1

  768. 	fabs	A2, A2

  769. 	fabs	A3, A3

  770. 	fabs	A4, A4

  771. 

  772. 	fsub	F1, A1, C1

  773. 	fsub	F2, A2, C2

  774. 	fsub	F3, A3, C3

  775. 	fsub	F4, A4, C4

  776. 

  777. 	fsel	C1, F1, C1, A1

  778. 	fsel	C2, F2, C2, A2

  779. 	fsel	C3, F3, C3, A3

  780. 	fsel	C4, F4, C4, A4

  781. 	.align 4

  782. 

  783. LL(107):

  784. 	andi.	r0,  N, 2

  785. 	beq	LL(108)

  786. 

  787. 	LFDUX	A1,    X, INCX

  788. 	LFDUX	A2,    X, INCX

  789. 	fabs	A1, A1

  790. 	fabs	A2, A2

  791. 	fsub	F1, A1, C1

  792. 	fsub	F2, A2, C2

  793. 	fsel	C1, F1, C1, A1

  794. 	fsel	C2, F2, C2, A2

  795. 	.align 4

  796. 

  797. LL(108):

  798. 	andi.	r0,  N, 1

  799. 	beq	LL(120)

  800. 

  801. 	LFDUX	A1,    X, INCX

  802. 	fabs	A1, A1

  803. 	fsub	F1, A1, C1

  804. 	fsel	C1, F1, C1, A1

  805. 	.align 4

  806. 

  807. LL(120):

  808. 	fpsub	F1,  C2, C1

  809. 	fpsub	F2,  C4, C3

  810. 

  811. 	fpsel	C1,  F1,  C1,  C2

  812. 	fpsel	C3,  F2,  C3,  C4

  813. 

  814. 	fpsub	F1,  C3, C1

  815. 	fpsel	C1,  F1,  C1,  C3

  816. 

  817. 	fsmtp	C2, C1

  818. 

  819. 	fsub	F1,  C2, C1

  820. 	fsel	C1,  F1,  C1,  C2

  821. 

  822.  	li	RET, 0

  823. 

  824. 	sub	XX, XX, INCX

  825. 

  826. 	srawi.	r0, NN, 3

  827. 	mtspr	CTR,  r0

  828. 	beq-	LL(126)

  829. 

  830. 	LFDUX	A1,    XX, INCX

  831. 	LFDUX	A2,    XX, INCX

  832. 	LFDUX	A3,    XX, INCX

  833. 	LFDUX	A4,    XX, INCX

  834. 

  835. 	fabs	T1, A1

  836. 	fabs	T2, A2

  837. 

  838. 	LFDUX	A5,    XX, INCX

  839. 	LFDUX	A6,    XX, INCX

  840. 	LFDUX	A7,    XX, INCX

  841. 	LFDUX	A8,    XX, INCX

  842. 	bdz	LL(123)

  843. 	.align 4

  844. 

  845. LL(122):

  846. 	LFDUX	A1,    XX, INCX

  847. 	fabs	T3, A3

  848. 	addi	RET, RET, 1

  849. 	fcmpu	cr0, C1, T1

  850. 	beq	cr0, LL(999)

  851. 

  852. 	LFDUX	A2,    XX, INCX

  853. 	fabs	T4, A4

  854. 	addi	RET, RET, 1

  855. 	fcmpu	cr0, C1, T2

  856. 	beq	cr0, LL(999)

  857. 

  858. 	LFDUX	A3,    XX, INCX

  859. 	fabs	T1, A5

  860. 	addi	RET, RET, 1

  861. 	fcmpu	cr0, C1, T3

  862. 	beq	cr0, LL(999)

  863. 

  864. 	LFDUX	A4,    XX, INCX

  865. 	fabs	T2, A6

  866. 	addi	RET, RET, 1

  867. 	fcmpu	cr0, C1, T4

  868. 	beq	cr0, LL(999)

  869. 

  870. 	LFDUX	A5,    XX, INCX

  871. 	fabs	T3, A7

  872. 	addi	RET, RET, 1

  873. 	fcmpu	cr0, C1, T1

  874. 	beq	cr0, LL(999)

  875. 

  876. 	LFDUX	A6,    XX, INCX

  877. 	fabs	T4, A8

  878. 	addi	RET, RET, 1

  879. 	fcmpu	cr0, C1, T2

  880. 	beq	cr0, LL(999)

  881. 

  882. 	LFDUX	A7,    XX, INCX

  883. 	fabs	T1, A1

  884. 	addi	RET, RET, 1

  885. 	fcmpu	cr0, C1, T3

  886. 	beq	cr0, LL(999)

  887. 

  888. 	LFDUX	A8,    XX, INCX

  889. 	fabs	T2, A2

  890. 	addi	RET, RET, 1

  891. 	fcmpu	cr0, C1, T4

  892. 	beq	cr0, LL(999)

  893. 	bdnz	LL(122)

  894. 	.align 4

  895. 

  896. LL(123):

  897. 	fabs	T3, A3

  898. 	fabs	T4, A4

  899. 

  900. 	addi	RET, RET, 1

  901. 	fcmpu	cr0, C1, T1

  902. 	beq	cr0, LL(999)

  903. 

  904. 	addi	RET, RET, 1

  905. 	fcmpu	cr0, C1, T2

  906. 	beq	cr0, LL(999)

  907. 

  908. 	fabs	T1, A5

  909. 	addi	RET, RET, 1

  910. 	fcmpu	cr0, C1, T3

  911. 	beq	cr0, LL(999)

  912. 

  913. 	fabs	T2, A6

  914. 	addi	RET, RET, 1

  915. 	fcmpu	cr0, C1, T4

  916. 	beq	cr0, LL(999)

  917. 

  918. 	fabs	T3, A7

  919. 	addi	RET, RET, 1

  920. 	fcmpu	cr0, C1, T1

  921. 	beq	cr0, LL(999)

  922. 

  923. 	fabs	T4, A8

  924. 	addi	RET, RET, 1

  925. 	fcmpu	cr0, C1, T2

  926. 	beq	cr0, LL(999)

  927. 

  928. 	addi	RET, RET, 1

  929. 	fcmpu	cr0, C1, T3

  930. 	beq	cr0, LL(999)

  931. 

  932. 	addi	RET, RET, 1

  933. 	fcmpu	cr0, C1, T4

  934. 	beq	cr0, LL(999)

  935. 	.align 4

  936. 

  937. LL(126):

  938. 	andi.	r0,  NN, 4

  939. 	beq	LL(127)

  940. 

  941. 	LFDUX	A1,    XX, INCX

  942. 	LFDUX	A2,    XX, INCX

  943. 	LFDUX	A3,    XX, INCX

  944. 	LFDUX	A4,    XX, INCX

  945. 

  946. 	fabs	T1, A1

  947. 	fabs	T2, A2

  948. 	fabs	T3, A3

  949. 	fabs	T4, A4

  950. 

  951. 	addi	RET, RET, 1

  952. 	fcmpu	cr0, C1, T1

  953. 	beq	cr0, LL(999)

  954. 

  955. 	addi	RET, RET, 1

  956. 	fcmpu	cr0, C1, T2

  957. 	beq	cr0, LL(999)

  958. 

  959. 	addi	RET, RET, 1

  960. 	fcmpu	cr0, C1, T3

  961. 	beq	cr0, LL(999)

  962. 

  963. 	addi	RET, RET, 1

  964. 	fcmpu	cr0, C1, T4

  965. 	beq	cr0, LL(999)

  966. 	.align 4

  967. 

  968. LL(127):

  969. 	andi.	r0,  NN, 2

  970. 	beq	LL(128)

  971. 

  972. 	LFDUX	A1,    XX, INCX

  973. 	LFDUX	A2,    XX, INCX

  974. 

  975. 	fabs	T1, A1

  976. 	fabs	T2, A2

  977. 

  978. 	addi	RET, RET, 1

  979. 	fcmpu	cr0, C1, T1

  980. 	beq	cr0, LL(999)

  981. 

  982. 	addi	RET, RET, 1

  983. 	fcmpu	cr0, C1, T2

  984. 	beq	cr0, LL(999)

  985. 	.align 4

  986. 

  987. LL(128):

  988. 	addi	RET, RET, 1

  989. 	.align 4

  990. 

  991. LL(999):

  992. 	li	r10, 16

  993. 	addi	SP, SP, -16

  994. 	mr	r3, RET

  995. 

  996. 	lfpdux	f27, SP, r10

  997. 	lfpdux	f26, SP, r10

  998. 	lfpdux	f25, SP, r10

  999. 	lfpdux	f24, SP, r10

  1000. 

  1001. 	lfpdux	f23, SP, r10

  1002. 	lfpdux	f22, SP, r10

  1003. 	lfpdux	f21, SP, r10

  1004. 	lfpdux	f20, SP, r10

  1005. 

  1006. 	lfpdux	f19, SP, r10

  1007. 	lfpdux	f18, SP, r10

  1008. 	lfpdux	f17, SP, r10

  1009. 	lfpdux	f16, SP, r10

  1010. 

  1011. 	lfpdux	f15, SP, r10

  1012. 	lfpdux	f14, SP, r10

  1013. 	addi	SP, SP,  16

  1014. 	blr

  1015. 

  1016. 	EPILOGUE