* Add preliminary implementation of WhereAmI()

As shown in #2538, default buffersizes on some platforms were smaller than required in memory.c
and the requirement could never be fulfilled for a calculated GEMM_R on PPC given the fomula used

Use wait-for-event to not spin in the blas_lock

The Arm implementation of rpcc() uses the architected timer
which is defined by the SBSA to be between 10-400MHz. These numbers
are much smaller than the cycle counter frequency used by x86. Make
the numbers closer by shifting the cycle counter up by the number of
leading zeros in the cntfrq_el0 register which gets us closer to a
noraml cpu clock cycle range.

Optimize RPCC function on ARM64

as I find conflicting information on accessibility from non-priviledged processes

* Add automatic fixups for OSX/IOS cross-compilation

* Add OSX/IOS cross-compilation test to Travis CI

* Handle platforms that lack hwcap.h by falling back to ARMV8

* Fix PROLOGUE for OSX/IOS

Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com>

Change the GEMM_P, GEMM_Q, GEMM_R values for Cortex A57

Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>

to be used on armv5 and new platforms

- use on arm, arm64 and any new platform
- use faster integer math instead of double
- use similar scale as rdtsc so that timeouts work

Optimizations for APM's xgene-1 (aarch64).

1) general system updates to support armv8 better.  Make all did not work, one needed to supply TARGET=ARMV8.
2) sgem 4x4 kernel in assembler using SIMD, and configuration changes to use it.
3) strmm 4x4 kernel in C.  Since the sgem kernel does 4x4, the trmm kernel must also do 4xN.

Added Dave Nuechterlein to the contributors list.

Signed-off-by: Timothy Gu <timothygu99@gmail.com>