Fix riscv64 detect

Signed-off-by: Han Gao <gaohan@uniontech.com>

Add dgemm kernel for arm64 SVE

* Add initial support for Fujitsu A64FX as generic ARMV8

* Add NO_AVX=1 fallbacks to newer generation x86_64 for completeness

* Update .travis.yml

1. Using core loongson3r3 and loongson3r4 for loongson
2. Add DYNAMIC_ARCH for loongson

Change-Id: I1c6b54dbeca3a0cc31d1222af36a7e9bd6ab54c1

Merge branch 'openblas-open-910' of git://github.com/damonyu1989/OpenBLAS into damonyu1989-openblas-open-910

Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266

Enable new build target platform -- COOPERLAKE. This target platform
supports all the SKYLAKEX supported ISAs + avx512bf16. So all the
SKYLAKEX specific kernels/drivers and related code are now extended
to be also active on COOPERLAKE. Besides, new BF16 related kernels
are active under this target.

This is the initial patch to support build infrastructure
for POWER10 architecture.

and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)

../config_kernel.h:24:9: warning: missing whitespace after the macro name
   24 | #define ARMV8-march armv8.2-a
      |         ^~~~~

The implementation is a hybird of the ARMV8 one with some of the
improved TX2 rountines along with specifying -march=v8.2-a

e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc

[WIP] Add support for Ampere EMAG8180 ARMV8 cpu