OpenBLAS

78 MB

Tree: f66ca05b31

Author	SHA1	Message	Date
Felix LeClair	05dce05c24	Update Makefile.riscv64 remove fast-math	8 months ago
Martin Kroeker	df87aeb5a2	Drop the -static Fortran flag from generic builds as it breaks OpenMP	1 year ago
Andrey Sokolov	73530b03fa	remove RISCV64_ZVL256B additional extentions	1 year ago
Andrey Sokolov	9c49a81d54	Resolve conflicts	1 year ago
kseniyazaytseva	e1afb23811	Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets * Fixed bugs in dgemm, [a]min\max, asum kernels * Added zero checks for BLAS kernels * Added dsdot implementation for RVV 0.7.1 * Fixed bugs in _vector files for C910V and RISCV64_ZVL256B targets * Added additional definitions for RISCV64_ZVL256B target	2 years ago
Octavian Maghiar	e4586e81b8	[RISC-V] Add RISC-V Vector 128-bit target Current RVV x280 target depends on vlen=512-bits for Level 3 operations. Commit adds generic target that supports vlen=128-bits. New target uses the same scalable kernels as x280 for Level 1&2 operations, and autogenerated kernels for Level 3 operations. Functional correctness of Level 3 operations tested on vlen=128-bits using QEMU v8.1.1 for ctests and BLAS-Tester.	1 year ago
Heller Zheng	0954746380	remove argument unused during compilation. fix wrong vr = VFMVVF_FLOAT(0, vl);	2 years ago
Heller Zheng	387e8970cd	Fix merge problem; Update compiling COMMON_OPT per review comments.	2 years ago
Heller Zheng	bef47917bd	Initial version for riscv sifive x280	2 years ago
Xianyi Zhang	968e1f51d8	Update RISC-V Intrinsic API.	3 years ago
damonyu	ef8e7d0279	Add the support for RISC-V Vector. Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266	5 years ago

11 Commits (f66ca05b313cf936eb8f75cc7ea1a87549e5b2a9)