Add CPUID data for Intel Denverton (as Nehalem)

xgetbv is function depends on NO_AVX being undefined - we could change that too, but that combo is unlikely to work anyway

Add cpuid for AMD Ryzen 2

fixes 1659

This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.

Add Bay Trail "Pentium N3520" atom

Add Braswell (extended model 4, model 12) N3150 as Nehalem

Second part of "support Intel Avoton via Nehalem kernel"

http://users.atw.hu/instlatx64/

Signed-off-by: Timothy Gu <timothygu99@gmail.com>

By default, OpenBLAS doesn't output the warning message. You can set
OPENBLAS_VERBOSE (e.g. export OPENBLAS_VERBOSE=1) to enable the warning
message on runtime.

The present patch verifies that, on machines declaring an Athlon CPU model and
family, the 3dnow and 3dnowext feature flags are indeed present. If they are
not, it fallbacks on the most generic x86 kernel. This prevents crashes due to
illegal instruction on qemu guests with a weird configuration.

Closes #272