12 Commits (670ec6f7576ecc74fff96be7c00ec8fffed8647b)

Author SHA1 Message Date
  gkdddd 670ec6f757 Added shgemm_kernel_8x8 for RISCV64_ZVL128B and shgemm_kernel_16x8 for RISCV64_ZVL256B 4 months ago
  Felix LeClair 05dce05c24
Update Makefile.riscv64 8 months ago
  Martin Kroeker df87aeb5a2
Drop the -static Fortran flag from generic builds as it breaks OpenMP 1 year ago
  Andrey Sokolov 73530b03fa remove RISCV64_ZVL256B additional extentions 1 year ago
  Andrey Sokolov 9c49a81d54 Resolve conflicts 1 year ago
  kseniyazaytseva e1afb23811 Fix BLAS and LAPACK tests for C910V and RISCV64_ZVL256B targets 2 years ago
  Octavian Maghiar e4586e81b8 [RISC-V] Add RISC-V Vector 128-bit target 1 year ago
  Heller Zheng 0954746380 remove argument unused during compilation. 2 years ago
  Heller Zheng 387e8970cd Fix merge problem; Update compiling COMMON_OPT per review comments. 2 years ago
  Heller Zheng bef47917bd Initial version for riscv sifive x280 2 years ago
  Xianyi Zhang 968e1f51d8 Update RISC-V Intrinsic API. 3 years ago
  damonyu ef8e7d0279 Add the support for RISC-V Vector. 5 years ago