Convert fldmia/fstmia instructions to UAL syntax for clang7

second part of fix for #1774, containing files missed in #1775

fixes #1774

Fix ARMV8 cross-compilation for IOS

Set USE_TRMM for all ZARCH variants to fix TRMM faults with zarch-gen…

fixes #1743

Add an AVX512 enabled DSYMV (L) function

Add an AVX512 enabled DGEMV (n)  function

Fix typo in sdot function

written in C intrinsics for best readability.
(the same C code works for Haswell as well)

For logistical reasons the code falls back to the existing
haswell AVX2 implementation if the GCC or LLVM compiler is not new enough

written in C intrinsics for best readability.
(the same C code works for Haswell as well)

For logistical reasons the code falls back to the existing
haswell AVX2 implementation if the GCC or LLVM compiler is not new enough

it looks like my previous pull request was short the final commit;
fix a typo in sdot

written in C intrinsics for best readability.
(the same C code works for Haswell as well)

For logistical reasons the code falls back to the existing
haswell AVX2 implementation if the GCC or LLVM compiler is not new enough

Add a AVX512 enabled SAXPY/DAXPY functions

written in C intrinsics for best readability.
(the same C code works for Haswell as well)

For logistical reasons the code falls back to the existing
haswell AVX2 implementation if the GCC or LLVM compiler is not new enough

written in C intrinsics for best readability.
(the same C code works for Haswell as well)

For logistical reasons the code falls back to the existing
haswell AVX2 implementation if the GCC or LLVM compiler is not new enough

written in C intrinsics for best readability.
(the same C code works for Haswell as well)

For logistical reasons the code falls back to the existing
haswell AVX2 implementation if the GCC or LLVM compiler is not new enough

Disable the 16x2 DTRMM kernel on SkylakeX as well

Disable the AVX512 DGEMM kernel for now

due to #1643

Fixed a few more unnecessary calls to num_cpu_avail.

* Return a somewhat sane default value for L2 cache size if cpuid returned something unexpected

Fixes #1610, the KVM hypervisor on Google Chromebooks returning zero for CPUID  0x80000006, causing DYNAMIC_ARCH
builds of OpenBLAS to hang

I don't have as many benchmarks for these as for gemm, but it should still
make a difference for small matrices.

this required switching to the generic gemm_beta code (which is faster anyway on SKX)
for both DGEMM and SGEMM

Performance for the not-retuned version is in the 30% range

This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.

Handle INCX=0,INCY=0 case

Fixes #1575 (sswap/dswap failing the swap utest on x86) as suggested by atsampson.

fixes #1571 (the old zrot.S assembly does not handle incx=0 correctly)

Revert " Switch mips32 target to USE_TRMM to fix complex TRMM"

... as it was just a silly workaround for the issue seen in #1563, caused by #1419

Remove extraneous brace from previous commit of mips dsdot fix

Revert changes from PR#1419

at least one of these changes apparently is an oversimplification, leading to TRMM breakage on some platforms as observed in #1563

Fixes #1561