17 Commits (41f9701ebcddc94d6f274249d516bad66ef8321a)

Author SHA1 Message Date
  Martin Kroeker d02c61e82e
Update lowercase cpunames for RISC-V 1 year ago
  Martin Kroeker 7228c708d7
Merge pull request #4461 from markdryan/cpuid_riscv64_crash 1 year ago
  Mark Ryan e0b610d01f Harmonize riscv64 LIBNAME for forced and non-forced targets 1 year ago
  Mark Ryan ec2aa32eb0 Fix crash in cpuid_riscv64.c 1 year ago
  Octavian Maghiar deecfb1a39 Merge branch 'risc-v' into img-riscv64-zvl128b 1 year ago
  Sergei Lewis 9edb805e64 fix builds with t-head toolchains that use old versions of the intrinsics spec 1 year ago
  Octavian Maghiar e4586e81b8 [RISC-V] Add RISC-V Vector 128-bit target 1 year ago
  Sergei Lewis 2406958629 * update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) 2 years ago
  Heller Zheng bef47917bd Initial version for riscv sifive x280 2 years ago
  Martin Kroeker ef9c976a94
Really fix compilation; fix crash when pmodel is not present in cpuinfo 3 years ago
  Martin Kroeker 30df29c0b3
Fix compilation 3 years ago
  Han Gao 8dd4579480 riscv: Fix machine recognition for c910v 3 years ago
  Martin Kroeker 46d22150de
Initial attempt at proper cpu detection on RISCV 3 years ago
  Han Gao 8123324c99 Fix riscv64 arch detect 3 years ago
  Xianyi Zhang fc35b72ae1 Refs #2899 4 years ago
  damonyu ef8e7d0279 Add the support for RISC-V Vector. 5 years ago
  Jerry Zhao c167a3d6f4 Added RISCV build 7 years ago