Modernize obsolete inline order

__loongarch_grlen and __loongarch_frlen were introduced in gcc version 8.3.0
(Loongnix 8.3.0-6.lnd.vec.31) internally within Loongson to standardize the
general and floating-point register widths. However, previous versions did
not have them, requiring additional checks to be added.

Work around miscompilation of zdot_thunderx2t99 by the current NVIDIA HPC compiler

Work around LLVM17 miscompiling the AVX512 microkernels for CASUM/ZASUM

Fix cooperlake and sapphire rapids march flags on clang

__builtin_vsx_assemble_pair was only in GCC 10-11.2 and was replaced by
__builtin_vsx_build_pair thereafter.

The march=cooperlake and march=sapphirerapids flags were never getting
added when building with Clang targetting those architectures. Instead
it was falling back to the skylake AVX512 implementation.

Clang added support for these two architectures in Clang 9 and Clang 12,
so introduce new checks for those versions to enable the appropriate
march flag, and fallback to skylake otherwise.

LoongArch64: Update dgemm kernel

Apply USE_TRMM to MIPS64_GENERIC as to GENERIC in gmake builds

LoongArch64: Add dgemv_t_8_lasx.S and dgemv_n_8_lasx.S

Enable use of AVX512 microkernels with NVIDIA HPC from version 22.3

Use SVE zgemm/cgemm on Arm(R) Neoverse(TM) V1 core

This patch removes the prefetches from cgemm/zgemm which improves the performance similar to sgemm/dgemm did in #3868, this means I'm happy to enable this on any applicable cores.

I also replicated the unrolling the copies from sgemm and dgemm.

Whilst disambiguating whilelt, I inadvertantly used the wrong datatype
for offsets, which can be negative. This rectifies that.

Use latest non-SVE kernels in ARMV8SVE

These are generally better and, in some cases, include threading which helps in the cores we're targeting here.