2 Commits (1093def0d1964109ca75e816b5df8ea0a5678a5b)

Author SHA1 Message Date
  Octavian Maghiar 4a12cf53ec [RISC-V] Improve RVV kernel generator LMUL usage 1 year ago
  Sergei Lewis 2406958629 * update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) 2 years ago