This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server)
target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set,
which brings 2 basic things:
1) 512 bit wide SIMD (2x width of AVX2)
2) 32 SIMD registers (2x the number on AVX2)

This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel
to AVX512VL; more will follow later but this patch aims to get the infrastructure
in place for this "later".

Full performance tuning has not been done yet; with more registers and wider SIMD
it's in theory possible to retune the kernels but even without that there's an
interesting enough performance increase (30-40% range) with just this change.

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

Blas 3 for single precision

Optimized Implementations for ThunderX2T99

Conflicts:
	CONTRIBUTORS.md

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

Improvements to Aarch64 kernels

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

optimized dgemm on power8 for 20 threads

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>

MIPS P5600(32 bit) and I6400(64 bit) cores support added.

Seperated mips and mips64 files.
Configurations support for mips 32 bit.

Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>