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@@ -1,5 +1,5 @@ |
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/***************************************************************************** |
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Copyright (c) 2011-2014, The OpenBLAS Project |
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Copyright (c) 2011-2015, The OpenBLAS Project |
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All rights reserved. |
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Redistribution and use in source and binary forms, with or without |
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@@ -30,49 +30,12 @@ OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE |
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USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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**********************************************************************************/ |
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/*********************************************************************/ |
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/* Copyright 2009, 2010 The University of Texas at Austin. */ |
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/* All rights reserved. */ |
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/* */ |
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/* Redistribution and use in source and binary forms, with or */ |
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/* without modification, are permitted provided that the following */ |
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/* conditions are met: */ |
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/* */ |
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/* 1. Redistributions of source code must retain the above */ |
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/* copyright notice, this list of conditions and the following */ |
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/* disclaimer. */ |
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/* */ |
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/* 2. Redistributions in binary form must reproduce the above */ |
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/* copyright notice, this list of conditions and the following */ |
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/* disclaimer in the documentation and/or other materials */ |
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/* provided with the distribution. */ |
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/* */ |
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/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */ |
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/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */ |
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/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ |
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/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ |
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/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */ |
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/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */ |
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ |
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/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */ |
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/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */ |
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/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ |
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ |
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/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ |
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/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ |
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/* POSSIBILITY OF SUCH DAMAGE. */ |
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/* */ |
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/* The views and conclusions contained in the software and */ |
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/* documentation are those of the authors and should not be */ |
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/* interpreted as representing official policies, either expressed */ |
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/* or implied, of The University of Texas at Austin. */ |
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/*********************************************************************/ |
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#ifndef COMMON_ARM64 |
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#define COMMON_ARM64 |
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#define MB |
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#define WMB |
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#define MB __asm__ __volatile__ ("dmb ish" : : : "memory") |
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#define WMB __asm__ __volatile__ ("dmb ishst" : : : "memory") |
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#define INLINE inline |
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@@ -81,17 +44,20 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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#ifndef ASSEMBLER |
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static void __inline blas_lock(volatile BLASULONG *address){ |
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/* |
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int register ret; |
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do { |
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while (*address) {YIELDING;}; |
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__asm__ __volatile__( |
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"1: \n\t" |
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"ldrex r2, [%1] \n\t" |
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"mov r2, #0 \n\t" |
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"strex r3, r2, [%1] \n\t" |
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"mov %0 , r3 \n\t" |
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"cmp r3, #0 \n\t" |
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"bne 1b \n\t" |
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"mov %0 , r3 \n\t" |
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: "=r"(ret), "=r"(address) |
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: "1"(address) |
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: "memory", "r2" , "r3" |
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@@ -100,7 +66,7 @@ static void __inline blas_lock(volatile BLASULONG *address){ |
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); |
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} while (ret); |
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*/ |
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} |
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@@ -166,3 +132,4 @@ REALNAME: |
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#endif |
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#endif |
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