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OpenBLAS/TargetList.txt

TargetList.txt 841 B
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Added docs for make TARGET=your_cpu_target.
14 years ago
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TargetList.txt: minor re-ordering
12 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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Init Sandybridge codes based on Nehalem.
13 years ago
Add HASWELL to TargetList.txt The Intel "Haswell" architecture is missing from the list of build targets.
11 years ago
Initial support for SkylakeX / AVX512 This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server) target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set, which brings 2 basic things: 1) 512 bit wide SIMD (2x width of AVX2) 2) 32 SIMD registers (2x the number on AVX2) This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel to AVX512VL; more will follow later but this patch aims to get the infrastructure in place for this "later". Full performance tuning has not been done yet; with more registers and wider SIMD it's in theory possible to retune the kernels but even without that there's an interesting enough performance increase (30-40% range) with just this change.
7 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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Refs #113. Fixed the typo BOBCATE -> BOBCAT
13 years ago
Added BULLDOZER target. So far it uses barcelona kernels.
13 years ago
Update the doc for target list.
11 years ago
added target processor STEAMROLLER
10 years ago
Add AMD Excavator target.
10 years ago
Add ZEN support (tested for auto-detected static backend)
8 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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Add POWER7/POWER8 as targets
10 years ago
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power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself
6 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
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MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
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Add MIPS 1004K target
7 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
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Added docs for make TARGET=your_cpu_target.
14 years ago
​
Init Sandybridge codes based on Nehalem.
13 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added mips I6500 core Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
8 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Added docs for make TARGET=your_cpu_target.
14 years ago
​
​
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
10 years ago
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Update the doc for target list.
11 years ago
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Add ARM targets.
10 years ago
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
9 years ago
Add ARM targets.
10 years ago
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
6 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
6 years ago
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ARM64: Add Cavium THUNDERX Target
8 years ago
ARM64: Add Cavium THUNDERX2T99 Target
8 years ago
add TARGET support for HiSilicon tsv110 CPUs
6 years ago
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
10 years ago
Add support for TARGET=ZARCH_GENERIC and TARGET=Z13
8 years ago
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Add Z14 target from patch provided by aarnez in #991
6 years ago
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  1. Force Target Examples:

  2. 

  3. make TARGET=NEHALEM

  4. make TARGET=LOONGSON3A BINARY=64

  5. make TARGET=ISTANBUL

  6. 

  7. Supported List:

  8. 1.X86/X86_64

  9. a)Intel CPU:

  10. P2

  11. KATMAI

  12. COPPERMINE

  13. NORTHWOOD

  14. PRESCOTT

  15. BANIAS

  16. YONAH

  17. CORE2

  18. PENRYN

  19. DUNNINGTON

  20. NEHALEM

  21. SANDYBRIDGE

  22. HASWELL

  23. SKYLAKEX

  24. ATOM

  25. 

  26. b)AMD CPU:

  27. ATHLON

  28. OPTERON

  29. OPTERON_SSE3

  30. BARCELONA

  31. SHANGHAI

  32. ISTANBUL

  33. BOBCAT

  34. BULLDOZER

  35. PILEDRIVER

  36. STEAMROLLER

  37. EXCAVATOR

  38. ZEN

  39. 

  40. c)VIA CPU:

  41. SSE_GENERIC

  42. VIAC3

  43. NANO

  44. 

  45. 2.Power CPU:

  46. POWER4

  47. POWER5

  48. POWER6

  49. POWER7

  50. POWER8

  51. POWER9

  52. PPCG4

  53. PPC970

  54. PPC970MP

  55. PPC440

  56. PPC440FP2

  57. CELL

  58. 

  59. 3.MIPS CPU:

  60. P5600

  61. 1004K

  62. 

  63. 4.MIPS64 CPU:

  64. SICORTEX

  65. LOONGSON3A

  66. LOONGSON3B

  67. I6400

  68. P6600

  69. I6500

  70. 

  71. 5.IA64 CPU:

  72. ITANIUM2

  73. 

  74. 6.SPARC CPU:

  75. SPARC

  76. SPARCV7

  77. 

  78. 7.ARM CPU:

  79. CORTEXA15

  80. CORTEXA9

  81. ARMV7

  82. ARMV6

  83. ARMV5

  84. 

  85. 8.ARM 64-bit CPU:

  86. ARMV8

  87. CORTEXA53

  88. CORTEXA57

  89. CORTEXA72

  90. CORTEXA73

  91. FALKOR

  92. THUNDERX

  93. THUNDERX2T99

  94. TSV110

  95. 

  96. 9.System Z:

  97. ZARCH_GENERIC

  98. Z13

  99. Z14

OpenBLAS is an optimized BLAS library based on GotoBLAS2 1.13 BSD version.